The present invention relates to an overcurrent detecting device for detecting an overcurrent flowing to a DC circuit and more particularly to a technique for setting a mask time of a detection of an overcurrent in a transient state to be short.
For example, in a DC circuit in which a semiconductor switch such as an FET is provided between a DC power supply and a load such as a motor or a lamp and is turned ON/OFF to control a driving operation of the load, there is provided an overcurrent detecting circuit for detecting an overcurrent such as a short-circuit current when it flows. When the overcurrent is detected, the semiconductor switch is broken instantly to protect the circuit.
FIG. 5 is a circuit diagram showing a structure of a load driving circuit mounting an overcurrent detecting circuit according to the related art. A DC power supply VB shown in FIG. 5 is a battery to be mounted on a vehicle, for example, and a load 101 is a motor for power window driving or various lamps which is/are to be mounted on the vehicle, for example. The DC power supply VB and the load 101 are connected to each other through an FET (T101) of an MOS type.
Moreover, an output terminal on a positive side of the DC power supply VB is set to have a voltage V1 and is grounded through a series connecting circuit including resistors R101 and R102. Accordingly, a voltage V4 of a node of the resistors R101 and R102 is obtained by dividing the voltage V1 through the resistors R101 and R102. The voltage V4 is supplied to an input terminal on a negative side of a comparator (CMP101).
Furthermore, the output terminal on the positive side of the DC power supply VB is grounded through a series connecting circuit including a resistor R103, an FET (T102) and a resistor R105, a node (a voltage V3) of the resistor R103 and the FET (T102) is connected to an input terminal on a positive side of an amplifier (AMP101), an input terminal on a negative side of the amplifier (AMP101) is connected to a source (a voltage V2) of the FET (T101), and an output terminal of the amplifier (AMP101) is connected to a gate of the FET (T102).
Moreover, a source (a voltage V5) of the FET (T102) is connected to the input terminal on a positive side of the comparator (CMP101).
Furthermore, a driver circuit 102 for driving the FET (T101) is provided. The driver circuit 102 is connected to a gate of the FET (T101) through a resistor R112. A numeric value described under each designation, for example, “20 K” described under the resistor R101 indicates that an example of a resistance value of the resistor R101 is 20 KΩ.
When the FET (T101) is turned ON, a voltage VDS between the drain and the source of the FET (T101) can be expressed in the following equation (1), wherein an ON-state resistance of the FET (T101) is represented by Ron and a drain current is represented by ID.VDS=V1−V2=Ron*ID  (1)
The amplifier (AMP101) outputs a control signal to the gate of the FET (T102) corresponding to a difference between the voltage VDS and a voltage generated on the resistor R103 and controls a current I1 flowing to a series circuit constituted by the resistor R103, T102 and R105. Consequently, a voltage generated on both ends of the resistor R103 is controlled to be equal to the voltage VDS between the drain and the source.
For example, furthermore, if a resistance value of a resistor R105 is set to have a magnitude which is 100 times as great as a resistance value of the resistor R103 (for example, R103=100Ω and R105=10 KΩ), the voltage V5 is obtained by amplifying the voltage VDS to be 100 times as great. This can be expressed in the following equation (2).
                                                                        V                ⁢                                                                  ⁢                5                            =                                                (                                      R                    ⁢                                                                                  ⁢                                          105                      /                      R                                        ⁢                                                                                  ⁢                    103                                    )                                *                VDS                                                                                        =                                                (                                      R                    ⁢                                                                                  ⁢                                          105                      /                      R                                        ⁢                                                                                  ⁢                    103                                    )                                *                Ron                *                ID                                                                        (        2        )            
The voltage V5 is supplied to the input terminal on the positive side of the comparator (CMP101) and the voltage (reference voltage) V4 obtained by dividing a voltage of the DC power supply VB through the resistors R101 and R102 is supplied to the input terminal on the negative side. When the voltage V5 is higher than the voltage V4, therefore, an output signal of the comparator (CMP101) is inverted. More specifically, when an overcurrent flows to the load 101 so that the current ID is increased, the voltage V5 is increased by the equation (2) and becomes higher than the voltage V4 so that an output signal of the comparator (CMP101) is inverted. By detecting the same signal to break the FET (T101), therefore, it is possible to protect the load 101 and a circuit to be connected thereto.
In the circuit, the ON-state resistance Ron is increased even if a load circuit is normal, and the voltage V5 is increased by the equation (2) so that V5>V4 is obtained and the output of the comparator (CMP101) is inverted from an L level to an H level for a transition period from an OFF state to an ON state of the FET (T101). Accordingly, an overcurrent detecting function cannot be achieved.
For this reason, there is provided a start timer 103 for starting synchronously with an output signal of the driver circuit 102 and an L level signal is output from the start timer 103 irrespective of the output of the comparator (CMP101) until the transition period of the FET (T101) is ended, and the L level output is used for determining an overcurrent. Thus, the transition period is prevented from being decided erroneously.
However, the related overcurrent detecting device has the following problems (1) and (2).
(1) A timer duration of the start timer 103 is set by previously estimating the transition period of the FET (T101). The transition period is not always equal but has a variation even if a unit having the same standards is used. For this reason, the timer duration should be set to be longer than a transition period having a maximum variation. In this case, if the FET (T101) having a shorter transition period than the set transition period is used, masking is carried out by the start timer 103 irrespective of the achievement of the overcurrent detecting function. As a result, there is generated a period for which the precious overcurrent detecting function cannot be used.
(2) When a type of the FET (T101) to be used as a semiconductor switch is changed, a gate capacity of the FET (T101) is varied so that the transition period is changed. Thus, the transition period is changed depending on a structure of a gate circuit or a gate characteristic of the FET. Correspondingly, a duration of the start timer 103 is to be set. With a structure in which the overcurrent detecting device is provided in an IC, it is necessary to add a regulating terminal for regulating the timer duration on the outside of the IC to an IC package and to add a regulating circuit to the outside of the IC. This causes an increase in a cost.